What NVIDIA’s Recent Patent Portfolio Reveals About Its Full-Stack Innovation Strategy

What NVIDIA's Recent Patent Portfolio Reveals About Its Full-Stack Innovation Strategy

White Paper by anovIP

Executive Summary

A review of recently published patent applications assigned to NVIDIA (Nov 2025–Jan 2026) reveals a strategy that is distinct from both "AI-software patenting" and traditional semiconductor patenting. NVIDIA is not simply patenting AI model features or isolated GPU hardware blocks. Instead, it is patenting compute primitives across the entire stack—from silicon reliability structures and memory-bandwidth shaping to ray-tracing pipelines, Gaussian rendering accelerators, dataset curation for foundation models, and even jailbreak detection for conversational AI systems.

The consistent theme is clear: NVIDIA patents the infrastructure of modern AI and graphics—the mechanisms that make large-scale inference, simulation, rendering, and deployment reliable, efficient, and commercially defensible.

Where Netflix patents streaming intelligence, Amazon patents cloud substrate, and Apple patents hardware embodiment, NVIDIA patents the acceleration layer—the specialized compute and orchestration techniques that power AI, graphics, and real-time simulation at scale.

1. NVIDIA's Core IP Philosophy: Own the Acceleration Layer

NVIDIA's competitive moat is not just "faster chips." It is an integrated acceleration platform spanning:
a) GPU/accelerator micro-architecture
b) Memory and bandwidth control
c) Rendering and ray tracing pipelines
d) Data center workload orchestration
e) AI model optimization and deployment
f) Dataset selection, simulation, and safety tooling

Its patent portfolio mirrors this. NVIDIA tends to avoid patenting "use cases" (e.g., "generate a 3D object") without also patenting the compute mechanisms that make the use case possible.

Strategic implication:

Even if competitors reproduce model architectures or applications, they still must solve the same underlying acceleration problems—where NVIDIA has increasingly defensible IP.

2. Next-Generation Rendering: Hardware for New Graphics Primitives

From triangles to Gaussians—patenting the next rasterization epoch

Graphics innovation is shifting from purely triangle-based pipelines toward new primitives and hybrid rendering approaches (including techniques aligned with Gaussian splatting and neural rendering trends). NVIDIA's patents show it is preparing for this transition at the silicon and pipeline level.

Representative patent publications & analysis

US 20260030840 – Hardware Accelerator for Gaussian Rendering and Reconstruction

Publication Number: US20260030840A1

Publication Date: January 29, 2026

Applicant: NVIDIA Corporation

Abstract: Rasterizers that include multiple processing elements each including logic specific to triangle rasterization, logic specific to Gaussian rasterization, and logic common to both of the triangle rasterization and the Gaussian rasterization. The rasterizer further includes a runtime-activated selector to activate either the logic specific to triangle rasterization or the logic specific to Gaussian rasterization.

First Indepedendent Claim: A rasterizer comprising:

a plurality of processing elements each comprising: logic specific to triangle rasterization;

logic specific to Gaussian rasterization;

logic common to both of the triangle rasterization and the Gaussian rasterization; and

a runtime-activated selector to activate either the logic specific to triangle rasterization or the logic specific to Gaussian rasterization.

What the publication covers

Why it matters

This is a foundational move: NVIDIA is patenting hardware-level support for alternative scene representations rather than treating Gaussian rendering as purely software.

Strategic insight:

By enabling runtime selection between triangle and Gaussian logic, NVIDIA positions the GPU as a universal rendering substrate for whatever representation dominates next.

US 20260017749 – Denoising Dynamically Ray-Traced Scenes Using Historical Pixel Values

Publication Number: US20260017749A1

Publication Date: January 15, 2026

Applicant: NVIDIA Corporation

Abstract: In various examples, systems and methods are disclosed relating to historical acceleration. One computer-implemented method includes determining at least one difference between first image data of at least one first buffer and second image data of at least one second buffer. The computer-implemented method further includes updating at least one of the first image data or the second image data based on the at least one difference.

First Indepedendent Claim: A computer-implemented method, comprising:

determining at least one difference between first image data of at least one first buffer and second image data of at least one second buffer; and

updating at least one of the first image data or the second image data based on the at least one difference;

wherein the at least one first buffer or the at least one second buffer corresponds to an update rate to expected image data of noisy input data.

What the publication covers

Why it matters

Ray tracing is compute-heavy; denoising is required for real-time viability. This patent protects temporal denoising mechanisms—a key factor behind perceived quality in RTX-style rendering.

US 20250384616 – Average Rate Regulator for Parallel Adaptive Sampler

Publication Number: US20250384616A1

Publication Date: December 18, 2025

Applicant: NVIDIA Corporation

Abstract: A ray tracing method forms a first accumulation of importance values of non-clamped pixels in an image and forms a second accumulation of waste importance of clamped pixels in the image. The first accumulation and the second accumulation are applied to set an updated average sample count for pixels in the image, and the ray tracer generates a number of sampling rays for particular pixels by applying the updated average sample count to a per-pixel importance setting.

First Indepedendent Claim: A graphics rendering system comprising:

a graphics display device;

one or more processor; and

logic to configure the processor to: form a first accumulation of importance values of pixels of an image for which ray trace sampling is not clamped (non-clamped pixels);

form a second accumulation of waste importance of pixels of the image for which the ray trace sampling is clamped (clamped pixels); and

apply the first accumulation and the second accumulation to adapt the average per-pixel sample count of a ray tracer.

What the publication covers

Why it matters

This patent targets the economics of ray tracing—where to spend samples to maximize image quality per compute budget.

3. 3D Generation, Texture Synthesis & Vision Pipelines

Patenting the bridge between generative AI and production graphics

NVIDIA's portfolio suggests it is building IP around production-grade 3D generation—not "text-to-3D" hype, but the compute workflows that align textures consistently across views.

Representative patent publications & analysis

US 20260030827 – 3D Object Generation with Text-Based Texture Alignment

Publication Number: US20260030827A1

Publication Date: January 29, 2026

Applicant: NVIDIA Corporation

Abstract: Various examples, systems, and methods are disclosed relating to texture synthesis. A first computing system determine, using a denoiser and based at least on an input indicating one or more characteristics of a scene, a plurality of estimated views of the scene corresponding to a texture. The first computing system can render, from a model of the texture, a plurality of renders of the texture, at least one render of the plurality of renders being associated with a corresponding estimated view of the plurality of estimated views. The first computing system can update the model of the texture based at least on the plurality of renders and the plurality of estimated views. The first computing system can update the plurality of estimated views based at least on the plurality of renders.

First Indepedendent Claim: One or more processors comprising:

one or more circuits to: determine, using a denoiser and based at least on an input indicating one or more characteristics of a scene, a plurality of estimated views of the scene corresponding to a texture;

render, from a model of the texture, a plurality of renders of the texture, at least one render of the plurality of renders being associated with a corresponding estimated view of the plurality of estimated views;

update the model of the texture based at least on the plurality of renders and the plurality of estimated views; and

update the plurality of estimated views based at least on the plurality of renders.

What the publication covers

Strategic insight

The hardest challenge in text-to-3D is not generating a mesh; it is maintaining coherent texture consistency across viewpoints. NVIDIA is patenting that consistency pipeline.

US 20260024217 – Optical Flow-Based Frame Interpolation to Synchronize Between Sensors

Publication Number: US20260024217A1

Publication Date: January 22, 2026

Applicant: NVIDIA Corporation

Abstract: In various examples, systems and methods are disclosed that perform motion detection across image frames, such as optical flow determination, to synchronize an asynchronous frame with respect to a target time for the asynchronous frame. For example, image frames from a sensor can be processed by an optical flow accelerator to detect displacement across the image frames, and the displacement can be used to interpolate a modified frame at the target time. This can be used to perform data collection and combining operations such as stitching and/or reconstruction. The synchronization can be performed from sensor data from sensors such as cameras, LIDAR sensors, and/or RADAR sensors.

First Indepedendent Claim: One or more processors comprising:

one or more circuits to: detect an asynchronous condition of sensor data from a sensor;

determine, responsive to detecting the asynchronous condition, motion associated with a first frame of the sensor data and a second frame of the sensor data;

generate a third frame based at least on the motion and the first frame; and

perform one or more operations associated with a machine based at least on the generated third frame.

What the publication covers

Why it matters

This sits at the intersection of perception and compute—critical for robotics, autonomous systems, XR, and sensor fusion pipelines.

4. Foundation-Model Data: Selection, Filtering, and Dataset Quality Control

Patenting the data flywheel, not just the model

One of the most strategically important shifts in AI is that model performance increasingly depends on dataset curation and enrichment. NVIDIA's patents show a clear recognition: data pipelines are now proprietary advantage.

Representative patent publications & analysis

US 20260023727 – Filters for Quality Control of Synthetically Generated Data

Publication Number: US20260023727A1

Publication Date: January 22, 2026

Applicant: NVIDIA Corporation

Abstract: In various examples, a system can include one or more processors to determine, using a plurality of retriever models, a quality score of each of a plurality of queries in a first dataset, determine, using a plurality of embedding models, a metric indicative of a relationship between each of the plurality of queries and the set of text information of the first dataset, and select one of the plurality of embedding models as a filter model based at least in part on correlation between the metrics outputted by the plurality of embedding models and the quality scores for the plurality of queries, the filter model applied to filter a plurality of queries and a plurality of sets of text information in a second dataset.

First Indepedendent Claim: A system, comprising one or more processors to:

determine, using a plurality of retriever models, a quality score of each of a plurality of queries in a first dataset, wherein the quality score is determined based at least on a number of the plurality of retriever models having retrieved a set of text information corresponding to each of the plurality of queries;

determine, using a plurality of embedding models, a metric indicative of a relationship between each of the plurality of queries and the set of text information of the first dataset; and

select one of the plurality of embedding models as a filter model based at least on correlation between the metrics outputted using the plurality of embedding models and the quality scores for the plurality of queries, the filter model applied to filter a plurality of queries and a plurality of sets of text information in a second dataset.

What the publication covers

Why it matters

Synthetic data is valuable—but only if filtered. NVIDIA is patenting filter selection logic for synthetic dataset quality.

US 20250384660 – Foundation Models for Multimodal Semantic Data Selection and Dataset Enrichment

Publication Number: US20250384660A1

Publication Date: December 18, 2025

Applicant: NVIDIA Corporation

Abstract: In various examples, a system can perform multimodal selection of data to generate and/or enrich efficient datasets. The system can retrieve clusters of image frames generated according to semantic characteristics, such as semantic embeddings, of the image frames. The system can selectively filter out image frames from the clusters that are visually similar to other image frames in the clusters, which can reduce the size of the resulting dataset while maintaining target amounts of semantic information in the dataset. The system can selectively add new image frames to the dataset, such as new image frames that have semantic differences from the images of the dataset. The system can update any of various AI models, such as to fine-tune a neural network-based model, suing the dataset.

First Indepedendent Claim: One or more processors comprising processing circuitry to:

generate, using one or more neural networks, (i) a semantic embedding of one or more image frames of a plurality of image frames and (ii) a visual embedding of each of the one or more image frames of the plurality of image frames;

generate a plurality of clusters of the plurality of image frames according to the semantic embedding of each of the one or more image frames of the plurality of image frames; and

remove, from at least one cluster of the plurality of clusters, at least one image frame according to the visual embedding of the at least one image frame and at least one other image frame of the at least one cluster to provide a dataset comprising the plurality of image frames remaining from the plurality of clusters.

What the publication covers

Strategic insight

This is an IP claim over multimodal dataset compression without performance collapse—highly valuable for training economics.

5. Model Optimization & Deployment as a Compute System

Latency-aware pruning, tokenization, and containerized deployment

NVIDIA's patents emphasize that the real "AI moat" is not training alone—it is efficient inference and deployability.

Representative patent publications & analysis

US 20250384238 – Joint Channel, Layer, and Block Pruning According to Latency Constraints

Publication Number: US20250384238A1

Publication Date: December 18, 2025

Applicant: NVIDIA Corporation

Abstract: In various examples, systems and methods are disclosed relating to jointly pruning channels, layers, and/or blocks of neural networks according to target latency constraints. One or more circuits can determine a plurality of importance scores for a plurality of layers of a neural network and can generate a latency cost data structure for the neural network. The one or more circuits can prune the neural network based at least on the plurality of importance scores, the latency cost data structure, and a target latency value.

First Indepedendent Claim: One or more processors comprising:

one or more circuits to: determine a plurality of importance scores for a plurality of layers of a neural network;

generate a latency cost data structure for the neural network; and

prune the neural network based at least on the plurality of importance scores, the latency cost data structure, and a target latency value.

What the publication covers

Why it matters

This patent protects model slimming with hardware-aware constraints—a core necessity for deploying models on GPUs and edge devices.

US 20250384588 – Joint Image and Video Tokenization with Causal Variational Autoencoder

Publication Number: US20250384588A1

Publication Date: December 18, 2025

Applicant: NVIDIA Corporation

Abstract: Video compression systems based on a variational autoencoder, the variational autoencoder including an encoder and a decoder coupled via a latent space embedding component, the encoder configured to transform an input video into a feature maps of the input video at different feature resolution scales, the latent space embedding component configured to transform the feature maps into a latent space parameter distribution, and the decoder configured to sample the latent space parameter distribution to generate a compressed version of the input video.

First Indepedendent Claim: A video compression system comprising a variational autoencoder, the variational autoencoder comprising:

an encoder and a decoder coupled via a latent space embedding component;

the encoder configured to transform an input video into a plurality of feature maps of the input video at different feature resolution scales;

the latent space embedding component configured to transform the feature maps into a latent space parameter distribution; and

the decoder configured to sample the latent space parameter distribution to generate a compressed version of the input video.

What the publication covers

Strategic insight

Tokenization is not just for text. NVIDIA is protecting video tokenization infrastructure, which underpins multimodal models and compression.

US 20250355656 – Model Customization and Deployment in Containerized Environments

Publication Number: US20250355656A1

Publication Date: November 20, 2025

Applicant: NVIDIA Corporation

Abstract: Various examples, systems, and methods are disclosed relating to a model customization pipeline. A first computing system can receive at least one customization of at least one artificial intelligence (AI) model corresponding to a base instance. The first computing system can generate a customized instance of the at least one AI model by updating the base instance of the at least one AI model based on the at least one customization. The first computing system can generate a software component configured to perform at least one operation using the customized instance of the at least one AI model. The first computing system can package the software component and the customized instance of the at least one AI model into a first container instance. The first computing system can deploy the software component within a runtime environment.

First Indepedendent Claim: A system, comprising:

one or more processors configured to: receive at least one customization of at least one artificial intelligence (AI) model corresponding to a base instance;

generate a customized instance of the at least one AI model by updating the base instance of the at least one AI model based on the at least one customization;

generate a software component configured to perform at least one operation using the customized instance of the at least one AI model;

package the software component and the customized instance of the at least one AI model into a first container instance; and

deploy the software component within a runtime environment.

What the publication covers

Why it matters

This is "MLOps in a box"—patenting how models are customized and deployed reliably in modern infra.

6. Data Center Orchestration: Scheduling as an AI Problem

Resource allocation becomes a learned control plane

NVIDIA's data center patents suggest a strategic shift: scheduling is evolving from heuristics to learning-driven orchestration.

Representative patent publications & analysis

US 20260023642 – Adaptive Allocation and Management of Processing Resources Using Dynamic Attention-Based Graph Neural Networks

Publication Number: US20260023642A1

Publication Date: January 22, 2026

Applicant: NVIDIA Corporation

Abstract: In various examples, systems, devices and methods are disclosed relating to management of processing resources and workloads assigned thereto. A system can obtain, from a plurality of processing resources executing a plurality of tasks, telemetry data and task assignment data. The system can perform generate, using the telemetry data and the task assignment data, a plurality of feature vectors, determine, using the plurality of feature vectors and a machine learning model employing a graph attention network (GAT) having a plurality of nodes, a performance state of a node of the plurality of nodes, and determine, based on the performance state of the node, an action to be taken to enhance performance of the plurality of processing resources or mitigate node failures. Each node can represent one or more respective processing resources and each feature vector can be associated with a respective node of the plurality of nodes.

First Indepedendent Claim: A system comprising:

a memory and one or more processing units to perform operations to: obtain, from a plurality of graphics processing units (GPUs) executing a plurality of tasks, GPU telemetry data and task assignment data, the task assignment data indicative, for at least one task of the plurality of tasks, of one or more respective GPUs executing the at least one task;

generate, using the telemetry data and the task assignment data, a plurality of feature vectors;

determine, using the plurality of feature vectors and a machine learning model employing a graph attention network (GAT) having a plurality of nodes, a performance state of at least one node of the plurality of nodes, wherein at least one node represents one or more respective GPUs of the plurality of GPUs and at least one feature vector of the plurality of feature vectors is associated with a respective node of the plurality of nodes; and

determine, based on the performance state of the at least one node, an action to be taken to enhance performance of the plurality of GPUs or mitigate node failures.

What the publication covers

Why it matters

This is patent protection over AI-native scheduling—a crucial differentiator in GPU clusters where utilization efficiency equals profit margin.

US 20250358228 – Dynamic Memory Bandwidth Shaping

Publication Number: US20250358228A1

Publication Date: November 20, 2025

Applicant: NVIDIA Corporation

Abstract: Bandwidth shaping mechanisms in a memory hierarchy operate a first bandwidth shaper on a first memory, such as a cache memory, to shape bandwidth to a second memory, such as a Dynamic Random Access Memory, and replenish the first bandwidth shaper from a second bandwidth shaper based on a hit bandwidth on the first memory.

First Indepedendent Claim: A process comprising:

operating a first bandwidth shaper on a first memory to shape bandwidth to a second memory; and

replenishing the first bandwidth shaper from a second bandwidth shaper based on a hit bandwidth on the first memory.

What the publication covers

Strategic insight

This patent speaks to the bottleneck of modern GPUs: memory bandwidth. NVIDIA is patenting how bandwidth is shaped and budgeted dynamically.

7. Reliability, Silicon Health & Optical Interconnects

Patenting what keeps high-performance systems alive

NVIDIA's portfolio includes strong "hard tech" patents that protect reliability and future interconnect pathways.

Representative patent publications & analysis

US 20250346114 – Die Crack Detection System

Publication Number: US20250346114A1

Publication Date: November 13, 2025

Applicant: NVIDIA Corporation

Abstract: An IC package includes a die and an elongate conductive trace formed adjacent to at least one peripheral edge of the die. Test logic in the package performs a die crack test by applying a test pattern to a first end of the conductive trace and sensing a response pattern at a second end of the conductive trace. The package is configured to operate in at least two distinct modes, including a manufacturing test mode in which a die crack test result is communicated from the package out of a JTAG port, and a field test mode in which the die crack test result is communicated from the package out of a data transfer port. A vehicle computer system may perform a fail safe action based on the die crack test result.

First Indepedendent Claim: A system, comprising:

a vehicle having a vehicle computer system and an integrated circuit package communicatively coupled to the vehicle computer system;

wherein the integrated circuit package is configured to perform a die crack test responsive to entering a field test mode and thereafter to produce a die crack test result;

wherein the integrated circuit package is configured to enter the field test mode upon power-up and is further configured to transmit the die crack test result to the vehicle computer system via a data transfer port of the integrated circuit package; and

wherein the vehicle computer system is configured to perform a fail safe action responsive to determining, based on the die crack test result, that the die in the integrated circuit package is cracked.

What the publication covers

Why it matters

Reliability is a commercial moat in enterprise GPUs. This patent protects packaging-level defect detection.

US 20250349628 – Silicon Structure to Monitor Bitcell Performance

Publication Number: US20250349628A1

Publication Date: November 13, 2025

Applicant: NVIDIA Corporation

Abstract: Silicon wafers including multiple wafer test structures, each comprising a ring oscillator comprising multiple bit-storing cells configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline. The oscillation frequency of the ring oscillator changes in accordance with the discharge rate of the bitlines, which is affected by factors such as word line under-drive and aging. The silicon wafers include at least one frequency monitor coupled to one or more of the ring oscillators.

First Indepedendent Claim: A circuit comprising:

a frequency monitor coupled to a ring oscillator; and

the ring oscillator comprising a plurality of bit-storing cells configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline.

What the publication covers

Strategic insight

NVIDIA is patenting predictive silicon aging and memory health monitoring, critical for long-lived deployments.

US 20260003123 – Stable Optical Waveguide and Method of Manufacturing the Same

Publication Number: US20260003123A1

Publication Date: January 1, 2026

Applicant: NVIDIA Corporation

Abstract: Some embodiments of the present disclosure are directed to an optical device including a stable optical waveguide loop and method of manufacturing the same. For example, an optical device (e.g., an optical ring resonator) may include a substrate and an optical waveguide loop formed on the substrate. The optical waveguide loop may define a path, where the optical waveguide loop may have an inner and outer radius that may be configured to be variable along the path of the optical waveguide loop. Further, a distance between the inner radius and a corresponding outer radius may define a width of the optical waveguide loop, where the width may be variable along the path of the optical waveguide loop. Additionally, or alternatively, the width may be configured to admit a plurality of higher order modes of light that may couple to a fundamental mode of light.

First Indepedendent Claim: An optical device, comprising:

a substrate; and

an optical waveguide loop formed on the substrate, wherein the optical waveguide loop defines a path, wherein the optical waveguide loop has an inner radius, and wherein the inner radius has a length that is variable along the path of the optical waveguide loop.

US 20250365073 – Dynamic Ring Assignment for Dense Wave Division Multiplexing Systems

Publication Number: US20250365073A1

Publication Date: November 27, 2025

Applicant: NVIDIA Corporation

Abstract: Mechanisms for tuning the optical resonator rings in an optical transmitter or an optical receiver involves reassigning one or more of the optical resonator rings to different laser lines, wherein the reassignment is based on mitigating an impact on energy consumption from adding or removing heat from the optical resonator rings to bring their resonant wavelengths coincident with the laser lines.

First Indepedendent Claim: A method comprising:

deactivating a first optical resonator ring that is closest to a laser source along a waveguide from among a plurality of optical resonator rings along the waveguide, the first optical resonator ring tuned to a first laser wavelength;

deactivating a second optical resonator ring of the plurality of optical resonator rings, the second optical resonator ring tuned to a laser wavelength adjacent to the first laser wavelength; and

beginning with the first optical resonator ring, setting resonant wavelengths of the optical resonator rings sequentially in an order determined by a spectral ordering of the optical resonator rings along the waveguide.

Why it matters

These publications signal investment in optical interconnects, relevant to data center scaling and chip-to-chip communication.

8. Safety & Governance for LLM Systems

Patenting operational safety, not just model performance

US 20250348580 – Jailbreak Detection for Language Models in Conversational AI Systems

Publication Number: US20250348580A1

Publication Date: November 13, 2025

Applicant: NVIDIA Corporation

Abstract: In various examples, systems and methods are disclosed relating to language model jailbreak detection using length-perplexity metrics. A system can identify a prompt for a language model—such as an LLM, VLM, etc.—and generate a perplexity score for the prompt. The system can determine, based at least on the perplexity score and a length of the prompt, that the prompt is indicative of a jailbreak attempt for the large language model. The system can restrict the prompt from input to the large language model—or block an output generated based on the prompt from being shared—responsive to determining that the prompt is indicative of the jailbreak attempt.

First Indepedendent Claim: One or more processors comprising:

one or more circuits to: compute a perplexity score for a prompt to a language model;

compute a length of the prompt;

determine, based at least on the perplexity score and the length, that the prompt is indicative of a jailbreak attempt of the language model; and

responsive to determining that the prompt is indicative of the jailbreak attempt, at least one of: restrict the prompt from input to the language model; or

restrict presentation of an output of the language model generated using the prompt as input.

What the publication covers

Strategic insight

This suggests NVIDIA is moving beyond compute to protect AI governance and safety mechanisms—critical for enterprise adoption.

9. The NVIDIA Pattern: Acceleration Compounds

Across all reviewed patents, a consistent pattern emerges:
a) NVIDIA patents compute primitives that scale across industries
b) Rendering, AI, and simulation converge into shared acceleration pipelines
c) Data quality, orchestration, and safety are treated as infrastructure
d) Hardware and software are co-designed—and co-protected

If Amazon is the operating system of the cloud, NVIDIA is the acceleration engine of modern computation.

Conclusion: Primitives Win Platforms

AI applications evolve weekly. Model architectures change yearly.

But compute primitives endure—the accelerators, pipelines, schedulers, bandwidth shapers, and reliability systems that make everything else possible.

NVIDIA's recent patents reveal a full-stack strategy to own the most defensible layer in the AI economy: how computation is accelerated.

How anovIP Can Assist

At anovIP, we help AI and semiconductor innovators build portfolios that protect compute primitives, not just product features—mirroring NVIDIA's system-first approach. We work with GPU, silicon, rendering, MLOps, and foundation-model teams to identify inventions worth patenting.